MoSys 1T-SRAM
® and 1T-FLASH™ technologies provide industry-leading benefits for system-on-chip (SoC) applications. These technologies are the result of many fundamental breakthroughs, involving dozens of patents and hundreds of staff-years of research and development.
1T-SRAM and 1T-FLASH Technology
MoSys's patented 1T-SRAM memory technology is based on a dynamic bit cell, which uses a single transistor and capacitor and achieves a considerable size advantage over six-transistor SRAMs (6T-SRAMs) and other conventional SRAM technologies. MoSys surrounds the bit cells with an array of architectural and circuit innovations to create a complete cost-effective, high-performance, low-power, portable and easy-to-integrate embedded memory solution.
Similarly, MoSys's patented 1T-FLASH technology is a more cost-effective, higher-performance alternative to conventional embedded non-volatile memory. Unlike other high-density flash alternatives, 1T-FLASH is implemented in a pure logic CMOS process, offering better economies and easier scalability to smaller process nodes.
Building a better embedded memory solution: MoSys 1T-SRAM starts
with a smaller bit cell, and surrounds it with innovative technology.
Additional Technologies
MULTIBANK® Architecture
MoSys's patented MULTIBANK architecture partitions 1T-SRAM and 1T-FLASH memory macros into many small banks, each capable of independent read, write and refresh operations. The small size of each bank allows the use of very short metal lines, resulting in extremely high performance. Additionally, the use of small independent banks allows active power to be greatly reduced, compared to architectures employing large unified structures.
Single-Cycle Pipelined Timing
1T-SRAM and 1T-FLASH internal timing is pipelined into a single clock cycle for a read or a write operation. This pipelining eliminates the need for the multiple clocks and complicated timing associated with other memory technologies, enabling 1T-SRAM to use a standard SRAM interface at the macro level.
Transparent Refresh
The refresh operations necessary to retain data on the dynamic bit cell operate transparently to the user. Depending on the application, 1T-SRAM can take advantage of unused cycle time or unused bandwidth to perform refresh operations. The MULTIBANK architecture further ensures that there is no performance penalty while the memory stays refreshed.
Leakage Reduction Circuitry
Because 1T-SRAM employs a dynamic bit cell with no direct leakage paths across the power rails, the current leakage is significantly lower than in embedded 6T-SRAM (less than a third in most cases). Through the use of optimized oxide, MoSys 1T-SRAM dramatically reduces gate oxide leakage.
Integrated ECC
All 1T-SRAM CLASSIC Macros and 1T-FLASH IP include MoSys patented TEC
® error correction circuitry as part of their design. This highly integrated error correction circuitry (ECC) allows MoSys memory macros to automatically correct hard and soft errors during the life cycle of the device, from manufacturing through field use. Since TEC operates continuously over all conditions, the reliability of 1T-SRAM CLASSIC Macros is ensured during all phases of operation. And in the case of 1T-SRAM, because repair is automatically handled by TEC, testing becomes a simple go/no-go test using standard test patterns, greatly simplifying this phase of manufacturing.
Dual-Port Architecture
In addition to its standard Single-Port 1T-SRAM, MoSys also offers dual-port architectures geared to the needs of high-resolution display drivers in mobile phones and other handheld devices.